library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_4_1_one_bit is
	port (
		in0 : in std_logic;
		in1 : in std_logic;
		in2 : in std_logic;
		in3 : in std_logic;
		sel : in std_logic_vector (1 downto 0);
		output : out std_logic
	);
end entity;

architecture behavioral of mux_4_1_one_bit is
signal aux_out : std_logic;

begin
	P1 : process (in0, in1, in2, in3, sel)
	begin
		case sel is
			when "00" =>
				aux_out <= in0;
			when "01" =>
				aux_out <= in1;
			when "10" =>
				aux_out <= in2;
			when "11" =>
				aux_out <= in3;
			when others =>
				aux_out <= in0;
		end case;
	end process;
	output <= aux_out;
end behavioral;
				